SerDes (serializers/deserializers) are devices that can take wide bit-width, single-ended signal buses and compress them to a few, typically one, differential signal ...
The paper describes the design-for-test (DFT) features of a 10.3125Gb/s Serdes and other such high datarate IP as XAUI, PCIe, and others. It is shown that extensive testability can be implemented in a ...
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